1. Field of the Invention
The present invention relates to a signal processing circuit for use in a charge generation type detection device, such as a pyroelectric sensor, an infrared sensor, and a pressure sensor, including a charge-voltage conversion circuit for converting a charge generated in the charge generation type detection device to a voltage.
2. Description of the Related Art
In recent years, in the field of surveillance camera apparatuses, object sorting apparatuses, and the like, there has been a demand for a system capable of performing a high-level information processing operation by obtaining information such as the position, the size, and the traveling speed of an object, as well as the number of objects and whether the object is in contact with another object. For example, in order to realize high level security, a surveillance camera apparatus is required to detect infrared radiation from a human to produce such information.
FIG. 8 illustrates a configuration of a conventional infrared radiation detection circuit 800 as an exemplary signal processing circuit of a charge generation type detection device.
The infrared radiation detection circuit 800 includes a charge-voltage conversion circuit 801 for converting a charge-generated in an infrared sensor 809 to a voltage. The charge-voltage conversion circuit 801 includes an input terminal 812, an output terminal 813 and a control terminal 814.
One terminal of the infrared sensor 809 is connected to a signal ground potential Vsg, and the other terminal thereof is connected to an input terminal 812 of the charge-voltage conversion circuit 801,
The charge-voltage conversion circuit 801 includes a capacitor 811 for storing a charge generated in the infrared sensor 809, an operational amplifier 810 which is connected to the capacitor 811 to form a feed-back loop, and a field effect transistor (hereinafter, referred to simply as xe2x80x9cFETxe2x80x9d) 802 as a reset switch which is connected in parallel with the capacitor 811.
The FET 802 is controlled according to a control voltage Vc applied to the control terminal 814. When Vc=VDD, the FET 802 is turned ON. Herein, VDD denotes a power supply voltage and VSS denotes a ground voltage. In this way, the FET 802 is repeatedly turned ON/OFF according to the control voltage Vc.
Thus, the charge-voltage conversion circuit 801 functions as a switched capacitor integration circuit (xe2x80x9cSC integration circuitxe2x80x9d).
An operation of the charge-voltage conversion circuit 801 will now be described.
When Vc=VDD, the FET 802 is turned ON, thereby initializing the charge-voltage conversion circuit 801 with the amount of charge in the capacitor 811 being reset to zero. In this case, an output voltage Vo at the output terminal 813 ss expressed by Expression (1) below.
xe2x80x83Vo=Vsgxe2x80x83xe2x80x83(1)
Then, when Vo=VSS, the FET 802 is turned OFF, thereby starting an operation of integrating the amount of charge being input from the infrared sensor 809 to the charge-voltage conversion circuit 801. When an amount of charge Q flows from the infrared sensor 809 into the charge-voltage conversion circuit 801 during a period in which the FET 802 is OFF, the output voltage Vo at the output terminal 813 is expressed by Expression (2) below.
Vo=Vsgxe2x88x92Q/C811xe2x80x83xe2x80x83(2)
Herein, C811 denotes the capacitance value of the capacitor 811.
Thus, the amount of voltage change xcex94Vo at the output terminal 813, which corresponds to the amount of charge Q generated in the infrared sensor 809 during d period in which the FET 802 is turned OFF, is expressed by Expression (3) below, based on Expressions (1) and (2).
xcex94Vo=xe2x88x92Q/C811xe2x80x83xe2x80x83(3)
Thus, the charge-voltage conversion circuit 801 can generate a voltage according to the amount of charge Q generated in the infrared sensor 809.
A parasitic capacitance exists in the FET 802 of the charge-voltage conversion circuit 801. As illustrated in FIG. 8, the parasitic capacitance of the FET 802 includes a parasitic capacitance 803 between the gate and the source of the FET 802 and a parasitic capacitance 804 between the gate and the drain of the FET 802. Herein, Cgs denotes the capacitance value of the parasitic capacitance 803 and Cgd denotes the capacitance value of the parasitic capacitance 804.
Transition of the FET 802 from ON to OFF (i.e., transition of the control voltage Vc applied to the control terminal 814) generates a clock feed-through in the FET 802. Due to the clock feed-through, a charge q is provided to one end of the capacitor 811 and another charge qo is provided to the output of the operational amplifier 810.
The charge q is expressed by Expression (4) below, and the charge qo is expressed by Expression (5) below.
q=xe2x88x92Cgsxc2x7(VDDxe2x88x92VSS)xe2x80x83xe2x80x83(4)
qo=xe2x88x92Cgdxc2x7(VDDxe2x88x92VSS)xe2x80x83xe2x80x83(5)
Due to the charge q, an offset voltage xcex94Voffset occurs at the output terminal 813. The offset voltage xcex94Voffset is expressed by Expression (6) below.
xcex94Voffset=Cgs/C811xc2x7(VDDxe2x88x92VSS)xe2x80x83xe2x80x83(6)
As can be seen from Expression (6), the offset voltage xcex94Voffset is a constant voltage. Since the offset voltage xcex94Voffset is added to the output voltage Vo the offset voltage xcex94Voffset becomes a DC offset voltage error in the output voltage Vo. The error has been A significant drawback to realization of high-sensitivity infrared radiation detection.
Moreover, the output of the operational amplifier 810 is designed to have the lowest impedance Zo among other devices connected to the output terminal 813. Therefore, all of the charge qo as shown in Expression (5) flows into the output of the operational amplifier 810. As a result, an offset voltage xcex94Voffset (t) occurs at the output terminal 813 due to the charge qo. The offset voltage xcex94Voffset (t) is expressed by Expression (7) below.
xcex94Voffset(t)=Zoxc2x7{∂(qo)/∂t}xe2x80x83xe2x80x83(7)
As can be seen from Expression (7), the offset voltage xcex94Voffset (t) Ls a transitional voltage which varies over time. The offset voltage xcex94Voffset (t) is high-frequency noise to the output voltage Vo. The high-frequency noise has been a significant drawback to realization of high-sensitivity infrared radiation detection.
Moreover, as the intensity of the infrared radiation increases, the amount of charge Q generated in the infrared sensor 809 also increases. In a region where the amount of charge Q is large, the output voltage Vo does not change according to Expression (2), resulting in a situation where the output voltage Vo is saturated to the level of the power supply voltage VDD or the ground voltage VSS. This has been a drawback to realization of an infrared radiation detection circuit having a wide dynamic range.
Furthermore, in order to realize an infrared radiation detection apparatus including a plurality of infrared sensors arranged in a one-dimensional or two-dimensional arrangement, the infrared radiation detection apparatus needs to include a plurality of charge-voltage conversion circuits. This increases the circuit scale of the infrared radiation detection apparatus, thereby making the apparatus high in cost and large in size.
In addition, external noise, particularly a 50 Hz or 60 Hz commercial frequency, may further be superimposed on the output voltage Vo, thereby reducing the infrared radiation detection capability. In order to reduce such noise, a filter circuit is used. However, it was not possible in the prior art to have such a filter circuit built in the charge-voltage conversion circuit. Therefore, the filter circuit had to be provided in a stage subsequent to the charge-voltage conversion circuit as a separate circuit from the charge-voltage conversion circuit. This has increased the circuit scale of the infrared radiation detection apparatus, thereby making the apparatus high in cost and large in size. The filter circuit could not be built in the charge-voltage conversion circuit because the capacitance value C811 of the capacitor 811 is small, whereby a resistor having a large enough resistance value to set the cut-off frequency of the filter circuit to a desired value could not be provided in the charge-voltage conversion.
The infrared radiation detection apparatus performs a chopping operation by alternately accepting and blocking the incoming infrared radiation at a low frequency of about 30 Hz. Thus, the infrared radiation detection signal will have the same frequency as the chopping frequency. When the operational amplifier of the charge-voltage conversion circuit employs a semiconductor circuit in which a switch, or the like, is provided by using a CMOS type transistor, the influence of flicker noise, i.e., 1/f noise, increases. When a switched capacitor circuit is employed, the influence of quantization noise increases. Thus, the signal-to-noise ratio is deteriorated, thereby lowering the detection capability.
According to one aspect of this invention, a signal processing circuit for a charge generation type detection device includes a charge-voltage conversion circuit for converting a charge generated in the charge generation type detection device to a voltage. The charge-voltage conversion circuit includes a first capacitor for storing the charge generated in the charge generation type detection device: an operational amplifier connected to the first capacitor to form a feed-back loop; and a first switch connected in parallel with the first capacitor for discharging the charge stored in the first capacitor. The first switch includes a first transistor for generating a first clock feed-through and a second transistor for generating a second clock feed-through, the first switch being configured so that at least a portion of the first clock feed-through is canceled by the second clock feed-through.
In one embodiment of the invention, the first switch is a CMOS type switch including a P-channel type transistor as the first transistor and an N-channel type transistor as the second transistor. The CMOS type switch is configured so as to satisfy Cpgs=Cngs and Cpgd=Cngd, where Cpgs denotes a gate-source capacitance of the P-channel type transistor, Cngs denotes a gate-source capacitance of the N-channel type transistor, Cpgd denotes a gate-drain capacitance of the P-channel type transistor, and Cngd denotes a gate-drain capacitance of the N-channel type transistor.
In one embodiment of the invention, the signal processing circuit further includes a circuit including a second capacitor and a second switch controlled according to a gain control voltage. The circuit is connected in parallel with the first capacitor.
In one embodiment of the invention, the signal processing circuit further includes a switched capacitor circuit connected in parallel with the first capacitor, the switched capacitor circuit functioning as a resister.
In one embodiment of the invention, the signal processing circuit further includes a feed-back circuit for feeding an output of the charge-voltage conversion circuit back to an input of the charge-voltage conversion circuit. The charge-voltage conversion circuit and the feed-back circuit are configured to have a delta/sigma modulation function.
In one embodiment of the invention, the feed-back circuit includes: a comparator for comparing an output voltage from the charge-voltage conversion circuit with a predetermined voltage; a delay element for delaying an output from the comparator; and a digital-to-analog converter for converting a digital signal output from the delay element to an analog signal.
According to another aspect of this invention, a signal processing circuit for a charge generation type detection device includes a charge-voltage conversion circuit for converting a charge generated in the charge generation type detection device to a voltage. The charge-voltage conversion circuit includes: a first capacitor for storing the charge generated in the charge generation type detection device: an inverter connected to the first capacitor to form a feed-back loop; and a first switch connected in parallel with the first capacitor for discharging the charge stored in the first capacitor.
In one embodiment of the invention, the first switch includes a first transistor for generating a first clock feed-through and a second transistor for generating a second clock feed-through, the first switch being configured so that at least a portion of the first clock feed-through is canceled by the second clock feed-through.
Thus, the invention described herein makes possible the advantages of: (1) providing a signal processing circuit for a charge generation type detection device having a reduced DC offset error in the output voltage and reduced high-frequency noise to the output voltage; (2) providing a signal processing circuit for a charge generation type detection device with which a wide dynamic range can be realized: (3) providing a signal processing circuit for a charge generation type detection device whose circuit scale can be reduced, and (4) providing a signal processing circuit for a charge generation type detection device having reduced 1/f noise and reduced quantization noise.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.